面向高性能DSP的一级可配置指令缓存设计与验证  

Design and verification of level-1 configurable instruction cache for high-performance DSP

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作  者:唐俊龙[1] 高睿禧 TANG Junlong;GAO Ruixi(School of Physics and Electronic Science,Changsha University of Science and Technology,Changsha 410114,China)

机构地区:[1]长沙理工大学物理与电子科学学院,长沙410114

出  处:《集成电路与嵌入式系统》2025年第5期24-34,共11页Integrated Circuits and Embedded Systems

基  金:湖南省制造业关键产品“揭榜挂帅”项目高性能高可靠国产DSP芯片项目(2022GXGG012)。

摘  要:针对程序运行中Cache无法有效预测非局部访问的问题,提出了一种基于二级存储结构的高安全性一级可配置指令缓存设计方案。该方案通过页与Cache行的两种粒度存储保护机制,确保不同级别用户的数据安全;实现了内部控制寄存器和灵活可配置的Cache/SRAM结构,支持快速配置和扩展;利用直接存储访问模块实现了与外部存储的高效交互。通过UVM平台进行模块级验证,并对比不同L1P大小配置下的命中率,调用40 nm低阈值库验证了系统的时延和功耗性能。实验结果表明,所设计的缓存方案能在32 KB至0 KB五种L1P配置间快速切换,满足600 MHz高性能DSP的需求,最大路径延时为1.47 ns,总功耗为309.577 mW。To address the issue of caches being unable to predict nonlocal program execution and prepare for critical tasks,this paper proposes a high-security,level-1 configurable instruction cache design.The design achieves flexible Cache/SRAM configurability through internal control registers.It ensures data access security for users at various levels through two granularity storage protection mechanisms:page-level and cache line-level.Rapid interaction with external storage data is achieved through direct memory access(DMA)to SRAM.A Universal Verification Methodology(UVM)verification platform is established to conduct module-level verification of the configurable instruction cache and collect coverage data.Different library functions are invoked to perform system-level verification and compare the hit rates of the cache under different L1P size configurations.A 40 nm low-threshold library is utilized to conduct post-simulation verification of latency and power consumption.The results demonstrate that the designed cache can safely and swiftly switch between five L1P configurations of 32 KB,16 KB,8 KB,4 KB,and 0 KB during program execution,with a maximum path delay of 1.47 ns and a total power consumption of 309.577 mW,meeting the stable operation requirements of a 600 MHz high-performance DSP.

关 键 词:一级指令缓存 UVM验证学 存储保护 DSP CACHE 

分 类 号:TP368[自动化与计算机技术—计算机系统结构]

 

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