基于RISC-V的LMS算法加速方案  

Acceleration scheme for LMS algorithms based on RISC-V

作　　者：叶岸茏 马令坤[1] 曲宗一 YE Anlong;MA Lingkun;QU Zongyi(College of Electronic Information and Artificial Intelligence,Shaanxi University of Science and Technology,Xi`an 710021,China)

机构地区：[1]陕西科技大学电子信息与人工智能学院,西安710021

出　　处：《集成电路与嵌入式系统》2025年第5期52-59,共8页Integrated Circuits and Embedded Systems

基　　金：国家自然科学基金重点项目—复杂信息链路下对非合作海洋声学监测网络的感知方法(62031021)。

摘　　要：LMS算法作为基本的自适应滤波算法,在噪声抑制领域得到了广泛应用,其实现方式主要基于通用处理器,但存在运算效率和性能较低的问题。RISC-V架构具有开源、精简、扩展性强等优势,适用于专用型处理器的实现。本文针对LMS算法设计了基于RISC-V的专用处理器。采用自定义指令集F扩展处理浮点数,并且在协处理器中加入MAC指令完成针对LMS算法的加速。实验结果表明,该处理器能够实现噪声的有效抵消,当输入信噪比为5 dB时,消噪后信噪比为17.5 dB;系统使用FPU执行LMS算法,指令执行数为220354,执行周期为586221;当采用本设计方案时,工作在FPU+MAC方式下,指令执行数为31621,执行周期为89412,效率明显提高。The Least Mean Square algorithm,as a typical adaptive filtering algorithm,has found extensive application in the field of noise suppression.Its implementation is mainly based on general-purpose processors,yet this method suffers from low computational efficiency and performance.The RISC-V architecture,with the advantages of open-source,streamlining,and scalability,is suitable for the implementation of dedicated processors.In this paper,a RISC-V based specialized processor is designed for the LMS algorithm.The customized instruction set F extension is used to process floating point numbers,and MAC instructions are added to the coprocessor to complete the acceleration of the LMS algorithm.The experiment results show that the processor can realize effective noise cancellation,when the input signal-to-noise ratio is 5 dB,the signal-to-noise ratio after noise cancellation is 17.5 dB.When the system uses FPU to execute the LMS algorithm,the number of instruction execution is 220354,and the execution cycle is 586221.When this design scheme is used,operating in FPU+MAC mode,the number of instruction execution is 31621,and the execution cycle is 89412,demonstrating a remarkable improvement in efficiency.

关 键 词：RISC-V 协处理器 LMS FPU 蜂鸟E203 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]