The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications  

作　　者：骆祖莹 闵应骅 杨士元 李晓维 

机构地区：Department of Automation, Tsinghua University, Beijing ,100084, China[1] Institute of Computing Technology, Chinese Academy of Sciences, Beijing ,100080, China[2]

出　　处：《Science in China(Series F)》2002年第6期401-405,共5页中国科学（F辑英文版）

基　　金：This work was supported by the National Natural Science Foundation of China (Grant No. 69733010); the 863 Project (Grant No. 2001AA111070).

摘　　要：The authors theoretically describe the monotonic increasing relationship between average powers of a CMOS VLSI circuit with and without delay. The power of an ideal circuit without delay, which can be fast computed, has been used as the evaluation criterion for the power of a practical circuit with delay, which needs more computing time, in such fields as fast estimation for the average power and the maximum power, and fast optimization for the low test power. The authors propose a novel simulation approach that uses delay-free power to compact a long input vector pair sequence into a short sequence and then, uses the compacted one to fast simulate the average (or maximum) power for a CMOS circuit. In comparison with the traditional simulation approach that uses an un-compacted input sequence to simulate the average (or maximum) power, experiment results demonstrate that in the field of fast estimation for the average power, the present approach can be 6-10 times faster without significant loss in accuracy (less than 3.5% on average), and in the field of fast estimation for the maximum power, this approach can be 6? times faster without significant loss in accuracy (less than 5% on average). In the field of fast optimization for the test power, the authors propose a novel delay-free power optimization approach for the test power. Experiment results demonstrate that, in comparison with the approach of direct optimization and the approach of Hamming distance optimization, this approach is of the highest optimization efficiency because it needs shorter time (16.84%) to obtain a better optimization effect (reducing 35.11% test power).The authors theoretically describe the monotonic increasing relationship between average powers of a CMOS VLSI circuit with and without delay. The power of an ideal circuit without delay, which can be fast computed, has been used as the evaluation criterion for the power of a practical circuit with delay, which needs more computing time, in such fields as fast estimation for the average power and the maximum power, and fast optimization for the low test power. The authors propose a novel simulation approach that uses delay-free power to compact a long input vector pair sequence into a short sequence and then, uses the compacted one to fast simulate the average (or maximum) power for a CMOS circuit. In comparison with the traditional simulation approach that uses an un-compacted input sequence to simulate the average (or maximum) power, experiment results demonstrate that in the field of fast estimation for the average power, the present approach can be 6-10 times faster without significant loss in accuracy (less than 3.5% on average), and in the field of fast estimation for the maximum power, this approach can be 6? times faster without significant loss in accuracy (less than 5% on average). In the field of fast optimization for the test power, the authors propose a novel delay-free power optimization approach for the test power. Experiment results demonstrate that, in comparison with the approach of direct optimization and the approach of Hamming distance optimization, this approach is of the highest optimization efficiency because it needs shorter time (16.84%) to obtain a better optimization effect (reducing 35.11% test power).

关 键 词：CMOS VLSI power estimation test power. 

分 类 号：TN405[电子电信—微电子学与固体电子学]