基于SHARC DSP芯片的并行加速板性能研究  

Research on the Performance of the Parallel Accelerating Board Based on the SHARC DSP Chip

作　　者：高曙[1] 孙元龙[2] 高洁[1] 

机构地区：[1]武汉理工大学计算机学院,武汉430063 [2]武汉数字工程研究所,武汉430074

出　　处：《计算机工程》2003年第1期23-25,共3页Computer Engineering

基　　金：国家自然科学基金项目(60173046);湖北省自然科学基金项目(2000j153)

摘　　要：分析了基于SHARC DSP芯片的并行加速板的组成、结构特点、工作原理；分别以著名的分形问题Mandelbrot Set和一个非线性瞬态热传导方程的多重网格并行算法的实现为例，对这种并行加速板的性能进行了研究；在带有这种并行加速板的多种计算机平台上测试了这两种并行算法的运行结果，表明这种加速板适用面广、性能稳定、功能强大、使用方便、运算速度快，具有很好的应用前景。Firstly, the paper analyses the structure and the working principle of the parallel accelerating board based on the SHARC DSP chip in detail. Secondly, the performance of the board is researched, which takes implementation of parallel algorithms for the famous mandelbrot Set and a non-linear transient heat transfer equation as examples. In the end, the efficiency of the parallel algorithms are tested respectively on the several computers with multibus or ISA, or PCI standard industrial bus, which are all composed of the boards. The result shows the parallel accelerating board can be plugged into a lot of computers, which have stable performance, powerful function, convenient usage and fast computation speed. It will has widespread prospect.

关 键 词：SHARCDSP芯片 并行加速板 性能 并行计算机系统 并行算法 CPU 

分 类 号：TP338.6[自动化与计算机技术—计算机系统结构]