一种基于总线的多处理器共享内存机制  

A Shared Memory Mechanism Based on Bus for Multi processor

作　　者：徐恪[1] 吴建平[1] 喻中超[1] 徐明伟[1] 

机构地区：[1]清华大学计算机科学与技术系,北京100084

出　　处：《小型微型计算机系统》2003年第3期321-326,共6页Journal of Chinese Computer Systems

基　　金：国家自然科学基金 (项目号 90 10 40 0 2和 6972 5 0 0 3 )资助;国家"863"重大项目(项目号 2 0 0 1AA12 10 13 )资助

摘　　要：基于总线的分布式多处理器体系结构是目前常见的高性能路由器硬件体系结构 .清华大学计算机系在研制“86 3”重大项目“高性能安全路由器”的过程中 ,在基于 Compact PCI总线的 Power PC多处理器平台上实现了一种多处理器共享内存机制 .该共享内存机制 (SM机制 )实现了一系列核心对象 ,包括 SM内存、SM信号量、SM消息队列和SM任务控制块等 .本文详细介绍了Multi processor distributed architecture based on bus is common hardware architecture for high performance router. Department of computer science of Tsinghua University develops a multi processor shared memory mechanism (SM) based on CompactPCI multi processor platform. SM is used in key project of national high technology research and development plan of China 'High Performance Security Router'. The SM mechanism includes several kernel objects such as SM memory, SM semaphore, SM message queue and SM task control block. We present the design and implementation of SM mechanism in details and show results of performance testing.

关 键 词：多处理器 共享内存机制 CPU COMPACTPCI总线 地址映射机制 消息通信 INTERNET 

分 类 号：TP332[自动化与计算机技术—计算机系统结构] TP393.4[自动化与计算机技术—计算机科学与技术]