CDPD系统RS码的FPGA设计与实现  

Design and Implementation of RS Encoding and Decoding on FPGA

作　　者：李晓春[1] 沈保锁[1] 

机构地区：[1]天津大学电子信息工程学院,天津300072

出　　处：《天津大学学报（自然科学与工程技术版）》2003年第2期220-224,共5页Journal of Tianjin University：Science and Technology

摘　　要：提出了使用现场可编程门阵列Altera公司的FLEX系列芯片实现CDPD系统中RS码的编码和解码方案,采用RS(63,47)进行纠错,结合FLEX器件改进大运算量环节,选用高效综合工具综合优化模块,在开发板上测试,完成了CDPD全双工RS编码和解码的要求,验证了该方案的可靠性,并为大规模集成电路的实现提供了源代码.In this article an approach to designing and implementing RS encoding and decoding in cellar digital packet data(CDPD) on ALTERA FLEX chip is presented.CDPD is a technology that provides digital packetswitched data services through standard analog cellular channels.CDPD adopts RS for error detecting and correcting.Based on the study RS encoding and decoding,some improvement has been made on the design and implementation on ALTERA FLEX chip.The efficient synthesis tool with the character of FLEX chip is made optimization.The performance of the approach is testified on hardware.It shows that the approach can accomplish the task of realtime duplex RS encoding and decoding and be prepared for implementation of VLSI.

关 键 词：RS编码 RS解码 可编程逻辑器件 

分 类 号：TN911.2[电子电信—通信与信息系统]