一种易于硬件实现的运动估计算法及其VLSI实现  

A block-matching algorithm based on hardware implementation and its VLSI architecture

作　　者：赵波[1] 杜建超[1] 颜尧平[1] 

机构地区：[1]西安电子科技大学综合业务网国家重点实验室,陕西西安710071

出　　处：《西安电子科技大学学报》2003年第2期160-164,共5页Journal of Xidian University

基　　金：国家自然科学基金资助项目(60002007)

摘　　要：综合考虑硬件成本和运动估计的精度,提出了一种易于硬件实现的运动估计算法,称之为分层准全搜索法.在串行输入以100%效率并行处理的硬件结构的基础上,进一步采用并行处理结构和流水线处理的方式,并结合了分层搜索的思想.所使用的硬件资源是全搜索法的四分之一,而且降低了系统时钟,从而降低了成本.实验结果表明算法得到的PSNR和全搜索匹配法可比,比其他快速搜索算法要好.文中结合H 263图像编解码器的实现,提出了一种并行处理时的数据存储方案,大大节省了片内存储器,从而又节省了系统功率和成本,已用FPGA实现了这种算法.Based on the cost of hardware implementation and the precision of estimation, a new blockmatching algorithm named the Hierarchical QuasiFull Search Algorithm (HQFSA) is proposed. HQFSA can be easily realized by hardware. A parallel architecture as well as a pipelining architecture is proposed based on onedimentional array processor with sequential inputs and processing with 100 percent efficiency. The HQFSA combines the main idea in the full search algorithm with that in the hierarchical block matching algorithm. The hardware cost of HQFSA is a quarter that of the full search algorithm. The clock frequency is reduced as a result of the parallel architecture. The experimental results show that the PSNR of HQFSA is comparable to that of the full search algorithm and better then that of the hierarchical block matching algorithm and other fast matching algorithms. We have also proposed an data memory scheme for reducing the cost based on the recommendation H263. We have already realized this algorithm using FPGA.

关 键 词：运动估计补偿 分层准全搜索法 并行处理 流水线 硬件结构 FPGA 数据存储 视频编码 

分 类 号：TN919.81[电子电信—通信与信息系统]