CPLD应用中VHDL的优化设计  

Optimization Design of VHDL in CPLD Appliance

作　　者：李若仲[1] 杨晓蓉[1] 李兆展[1] 

机构地区：[1]空军工程大学导弹学院,陕西三原713800

出　　处：《空军工程大学学报（自然科学版）》2003年第2期74-77,共4页Journal of Air Force Engineering University(Natural Science Edition)

基　　金：军队科研基金资助项目(Y9901)

摘　　要：VHDL语言的优化设计旨在充分利用CPLD所提供的硬件资源,使项目设计能适配到一定规模的CPLD芯片中,并提高系统的工作速度、降低系统功耗。优化的主要目标是减少适配所需要的宏单元数,对Lattice公司的芯片尤其是GLB的数目。实践证明,改变模块结构和描述方法、尽量使模块资源共享、对时序电路工作方式的变通性设计、触发器类型的选择等都是行之有效的优化方法,可在很大程度上改善项目的适配结果和系统的性能价格比,在CPLD的开发应用中具有很大的应用价值。The optimization design of VHDL is for the purpose of making full use of hardware resources provided by CPLD, making the item design suit to certain scale of CPLD chip, increasing the system speed and lowering the power-waste. The intention of optimization is to reduce adapted macrocell numbers, especially the GLE chip numbers of Lattice company. The fact shows that some optimization methods are effective in practice, such as changing the module structure and the method of description, making the module resources shared as much as possible, the versatility design of time-sequence electro-circuit working pattern and the selection of Flip-Flop types, etc. They can improve adaptation result of item and function price ratio to system, VHDL has great value in the exploitation and appliance of CPLD chips.

关 键 词：CPLD 硬件资源 优化设计 描述 性能价格比 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]