优化微程序控制器设计  

New Ways for Reducing Microcode ROM Area in Microprogrammed Processor

作　　者：朱霞[1] 高德远[1] 樊晓桠[1] 张盛兵[1] 

机构地区：[1]西北工业大学计算机科学与工程系,陕西西安710072

出　　处：《西北工业大学学报》2003年第2期176-179,共4页Journal of Northwestern Polytechnical University

基　　金：十五预研项目 (4 130 80 10 10 8)

摘　　要：大多数 CISC处理器和 VLIW处理器都采用微程序控制。在这些处理器中 ,微程序控制器的性能是决定整个处理器性能的关键因素之一。本文探讨微程序控制器的优化设计。分析如何提取公共微操作序列 ,提出设计寻址入口与功能入口的方法来减少微程序 ROM的深度 ;借鉴页式微程序管理的思想 ,提出页式微程序 ROM设计来减少微程序 ROM的位宽。优化设计之后 ,微程序控制器面积减少 2 8.90 %。In the design of microprogrammed processor, mostly VLIW or CISC processors, reduction of microcode ROM area is performance critical as long as such reduction does not lower the speed to an impermissible level. We propose two new methods for reducing microcode ROM area. One new method is the reduction of the depth of microcode ROM; section 2 explains how this reduction is achieved through proper design of addressing entry and function entry; to the best of our knowledge, we have not seen any paper on reducing depth of microcode ROM in the open literature. Another new method is the reduction of the width of microcode ROM; section 3 explains how this reduction is achieved through the proper design of a paged microcode ROM; we have seen papers in the open literature on reducing width of microcode ROM but they are all different from the way of reduction in section 3. We have applied both of our new methods to a microprocessor design as explained in detail in section 4; reduction of the microcode ROM area is as much as 28.9%; microprocessor speed before and after reduction of microcode ROM area are 28.6MHz and 26.2MHz respectively, both above the permissible minimum speed of 25MHz.

关 键 词：微程序设计 寻址入口 功能入口 页式微程序ROM 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]