VHDL语言在寄存器描述中两个局限性的探讨  

Two Restricts to Registers Description through VHDL Programs

作　　者：付扬[1] 杨旭[1] 田雪[1] 

机构地区：[1]辽宁石油化工大学信息工程学院,辽宁抚顺113001

出　　处：《控制工程》2003年第3期279-281,共3页Control Engineering of China

摘　　要：通过VHDL编程中对寄存器RTL描述限制的深入分析和探讨,提出了利用一个扫描控制信号来完成对多个寄存器描述的间接描述方法,即在扫描时钟信号的边沿监测下,输入信号和在前一周期边沿接收的输入信号比较,若不相等,则说明此时输入信号发生了一个边沿事件,即可等效为寄存器的描述,并给出了具体语句。通过实例证明,该方法克服了对寄存器描述的限制,具有一定的创新性、实用性和推广价值。The restricts to registers description t hrough VHDL programs were analysed and discussed.It poses indirect method that u sing a control signal fi nishing description to many registers. Under supervising of scan clock signal co mparing inpu t signal and itsreceived input signal last period, if they are not equal , it shows that there happens an edge event this moment, which can be equal to registers description and give specific language. Through examples, synthetic result shows that the method ove r comes restricts to registers describe and has certainly new ideas, practical nat ure and spreading value.

关 键 词：寄存器 局限性 VHDL语言 硬件描述语言 电路设计 

分 类 号：TP332.11[自动化与计算机技术—计算机系统结构] TP312[自动化与计算机技术—计算机科学与技术]