全通路图法用于CMOS开关级形成测试  

Using the Whole Path Graphs ( WPGs ) Method for Generating Tests of CMOS Switch Level

作　　者：梁业伟[1] 

机构地区：[1]北京计算机学院

出　　处：《计算机辅助设计与图形学学报》1989年第1期70-74,共5页Journal of Computer-Aided Design & Computer Graphics

摘　　要：文中主要探讨全通路图法推广运用于MOS电路时要考虑的一些特点。采用的故障模型是逻辑线的固定断路故障和通路故障,stuck-open(on)和s.a.o(1)故障仅是它的子集,它代表了实际使用中出现的大多数故障。由于“糖葫芦串”式的通路图和MOS电路基本上是一一对应的关系,所以在开关级形成测试其计算复杂性不会比门级高。这一点更突出体现在CMOS中。由于全通路图法可以用于它,所以该法过去已有的结论基本上全可用。这样,还可以考虑检测多故障的问题。An application of the WPGs Method in generating tests for CMOS switch level is described in this paper. Permanent line breaks and shorts are used to represent faults in a circuit. A line break fault is a fault which breaks a logic line so that conduction through the line is no longer possible. A line short fault is a fault which shorts the two terminals of a logic line so that the line is always conducting. The fault model is an extension of stuck-open (on), s.a.o (1), and can represent most of the possible failures observed in field practice. Cluster Shaped Logic Path Graphs (CLPGs) are analogous to connection grahps in[4]. One point to note is that CLPGs are subgraphs of CLuster WPGs, therefore we can use the concept of WPGs to detect multiple faults.

关 键 词：全通路图法 CMOS 电路 测试 

分 类 号：TN707[电子电信—电路与系统]