高安全性的智能卡芯片结构与设计  

High security smart card architecture and design

作　　者：周宏华[1] 李树国[1] 周润德[1] 

机构地区：[1]清华大学微电子学研究所,北京100084

出　　处：《清华大学学报（自然科学版）》2003年第4期569-572,共4页Journal of Tsinghua University(Science and Technology)

基　　金：国家自然科学基金资助项目 ( 5 9995 5 5 0 -0 1)

摘　　要：为适应信息安全系统的要求 ,提出一种高安全性的智能卡芯片结构 ,并进行了设计实现。通过集成 8位微处理器内核、 RSA用加解密协处理器和大容量的片内 Flash存储器 ,以及存储器访问控制电路和专用的硬件安全电路 ,实现了系统的整体安全可靠性。该结构采用 TSMC公司0 .35 μm 的 CMOS工艺设计和制造 ,可以在 374 ms完成 10 2 4位 RSA运算 ,实现数字签名和身份认证 ,并能有效地防止非法操作、 DPA (deferential power analysis)分析等常见的攻击 ,适用于电子商务。A new smart card chip architecture was developed with very high security for information security systems. The chip integrates an 8 bit microprocessor core, RSA cryptographic coprocessors and a large on chip Flash memory, together with memory access control logic and dedicated security circuits to improve the smart card's resistance against well known attacks, such as voltage/clock analysis and DPA (deferential power analysis) attacks. The architecture was implemented in 0.35 μm CMOS technology of TSMC. The algorithm takes about 374 ms to complete a 1 024 bit RSA computation, so digital signatures and authentication are supported. The chip's high security and flexibility make it very suitable for use in electronic business systems, social security card systems and other fields.

关 键 词：智能卡芯片 芯片结构 芯片设计 信息安全系统 模乘器 安全逻辑 数字签名 

分 类 号：TN492[电子电信—微电子学与固体电子学]