应用于并行ADC性能扩展的一种比特滑动流水模数转换方法研究  

Research of bits' gliding pipeline A/D converterapplied to parallel ADC

作　　者：潘志铭[1] 王百鸣[1] 

机构地区：[1]深圳大学信息工程学院,广东深圳518060

出　　处：《半导体技术》2003年第6期29-32,共4页Semiconductor Technology

基　　金：深圳市2002年科技计划资助

摘　　要：根据现代通信对模数转换的高速、高分辨率性能要求,在对现有的并行式模数转换电路研究和改进的基础上,提出了一种比特滑动流水并行式模数转换方法,从而简化了电路结构、节省了器件、降低了功耗,更有利于集成化。时域仿真实验结果表明,运用该方法实现的ADC,其采样频率达到10Ms/s。According to the high speed and high resolution performance requirement of A/D conversionrequired by modern communication, on the basis of the research and improvement of current parallel ADC,a method of bits' gliding pipeline A/D conversion is presented. This method can provide a more simplystructure, fewer components and lower power consumption than the current ones, and then it can be betterfor integration. It is proved by the result of time domain simulation that, by applying this method thesampling frequency of the ADC can reach 10Ms/s.

关 键 词：模数转换方法 并行转换 比特滑动 ADC 分段量化 电路设计 仿真 

分 类 号：TN792[电子电信—电路与系统]