一种1.25 Gbps CMOS以太网串并/并串转换电路  

A 1.25 Gbps CMOS Serializer/Deserializer for Ethernet

作　　者：郭亚炜[1] 张占鹏[1] 章奕民 邱祖江 杨莲兴[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433 [2]Vaishali Semiconductor LLC [3]上海敏勤电子技术有限公司,上海200001

出　　处：《微电子学》2003年第1期53-55,59,共4页Microelectronics

摘　　要：　用0.35μmCMOS工艺实现了单芯片1.25Gbps千兆以太网串并/并串转换电路。该电路兼容ANSI的光纤信道物理层标准(FC-0)。与同类电路相比,其核心单元—并串转换电路和串并转换电路—具有结构简单、面积小的优点[1,2],其高速串行数据随机抖动只有同类电路的一半。另外,电路中还集成了锁相环环路滤波电容。A monolithic 125 Gbps Serializer/Deserializer (Serdes) for Gigabit Ethernet is fabricated in 035 μm CMOS process with double polysilicon and triple metal layers This transceiver is compatible with the fiber channel physical layer (FC0) standard The critical cell of this chip,serializer & deserializer, is simpler and smaller than the previously reported circuit The highspeed serial data has a random jitter only half of the previous reports Loop filters for the phase locked loop are integrated into the chip 

关 键 词：CMOS 以太网 串并/并串转换电路 锁相环 光纤通信 

分 类 号：TN929.11[电子电信—通信与信息系统] TN432[电子电信—信息与通信工程]