Design of On—Chip Clock Generation with 50／50 Duty Cycle Correction  

作　　者：HANYueqiu CUIWei CHENHe 

机构地区：[1]DepartmentofElectronicEngineering,BeijingInstituteofTechnology,Beijing,Beijing100081,China

出　　处：《Chinese Journal of Electronics》2003年第1期144-146,共3页电子学报（英文版）

摘　　要：A circuit design of on-chip clock generation which improves the duty cycle performance and prevents latch-up effect is described.The circuity provides onchip clock with automatic duty cycle correction so as to overcome the shortcoming of clock duty cycle dependence on technology parameters of the traditional on-chip clock generation circuit.It is extremely important that the dynamic power consumption equals approximately the one of its predecessor.The effective performance of the proposed circuit is confirmed by SPICE simulation.

关 键 词：非稳态多谐振荡器 时钟发生器 占空因数 片上系统 集成电路 

分 类 号：TN752[电子电信—电路与系统]