基于FPGA的串行维特比译码的实现  

Implementation of Serial Viterbi Decoding Based on FPGA

作　　者：陈春霞[1] 王匡[1] 

机构地区：[1]浙江大学信电系,杭州310027

出　　处：《计算机工程》2003年第14期169-171,共3页Computer Engineering

摘　　要：维特比算法是一种卷积码译码算法。随着卷积码约束度的增加，并行维特比译码所需的硬件资源呈指数增长，限制其硬件实现。该文讨论了一种串行译码结构的FPGA实现方案。这种串行结构适合长约束度的卷积码译码，能在性能不下降的前提下有效地节省资源。Viterbi algorithm is applicable to decoding of convolutional codes. The hardware consumption of parallel Viterbi decoding shows exponential increase with the increase of constraint length of convolutional codes, which limits its hardware implementation. In this paper, the FPGA implementation of a serial Viterbi decoding architecture is presented. Suitable for decoding convolutional codes with long constraint length, this architecture saves hardware resource without performance deterioration.

关 键 词：卷积码 约束度 申行维特比译码 FPGA 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]