适于消谐模型求解的矩阵乘法器设计与实现  

Design and Implementation of Matrix Multiplier for Inverter Harmonic Elimination Model Calculation

作　　者：吴淑泉[1] 王前[1] 谢运祥[2] 

机构地区：[1]华南理工大学电子与信息学院,广东广州510640 [2]华南理工大学电力学院,广东广州510640

出　　处：《华南理工大学学报（自然科学版）》2003年第8期1-5,共5页Journal of South China University of Technology(Natural Science Edition)

基　　金：国家自然科学基金资助项目 (5 0 0 0 70 0 1)

摘　　要：在求解逆变器消谐PWM模型的迭代运算中 ,需要进行大量的矩阵乘法运算 .为了提高运算速度 ,笔者在论述矩阵运算并行算法的基础上 ,提出了基于二维正方形心动阵列结构的矩阵乘法器 ,并研究了二维方阵结构的矩阵乘法器的FPGA硬件实现方法 ,比较了单处理机乘法器和二维方阵结构的矩阵乘法器的运算速度及所需器件资源 ,结果表明采用二维正方形心动阵列实现的矩阵乘法器 ,具有高度并行性和流水线性特点 ,可使阵列中负载均匀 ,延时缩短 ,有利集成度提高 。A large quantity of matrix multiplier calculations must be executed in the iterative calculation of the inverter harmonic elimination PWM model. In order to fasten the calculation speed, a matrix multiplier, which is based on 2-D square systolic array architecture, is introduced in this paper in light of the parallel algorithm of matrix computation. The implementation of this matrix multiplier used by FPGA is analyzed and a comparison is made in terms of the computation speed and occupied hardware resources between the single processing element matrix multiplier and the 2-D square systolic array architecture matrix multiplier. The research results show that the matrix multiplier based on 2-D square systolic array architecture possesses advantages of parallel processing and flow computation. It can unify the load, shorten the delay and increase the level of integration. It has proved to be a good algorithm of matrix multiplier computation with regard to the inverter harmonic elimination model calculation.

关 键 词：消谐模型 矩阵乘法 心动阵列 

分 类 号：TM92[电气工程—电力电子与电力传动]