一种有效的VLSI平面时钟布线算法  

An Efficient VLSI Planar Clock Routing Algorithm

作　　者：李海军[1] 严晓浪[1] 马琪[1] 

机构地区：[1]杭州电子工业学院微电子CAD研究所,浙江杭州310012

出　　处：《电路与系统学报》2003年第4期63-67,共5页Journal of Circuits and Systems

摘　　要：本文提出了一种有效的VLSI平面时钟布线算法,通过自顶向下的对时钟汇点交替的进行水平和垂直划分,然后自底向上的沿着切割线方向对两棵子树进行合并来构造一棵平面时钟树,在构造时钟树的同时完成线网的连接。最后采用启发式的障碍避免算法使线网绕开障碍物。An efficient VLSI planar clock routing algorithm is proposed. At first, the clock sinks are partitioned alternately by horizontal lines and vertical lines from the top to the bottom, then a planar clock tree is constructed by merging two sub-trees along the cut line in a bottom-up way. All the wires are connected after the clock tree is successfully constructed. Finally, a heuristic algorithm is proposed to move the wires out of the obstacles.

关 键 词：时钟布线 时钟树 拓扑生成 实体嵌入 

分 类 号：TN405.97[电子电信—微电子学与固体电子学]