宽带数字下变频器的一种新的实现结构  

A Novel Implementation Architecture for Wideband Digital Down-Converter

作　　者：张玉良[1] 吴伟陵[1] 田宝玉[1] 

机构地区：[1]北京邮电大学,181信箱北京100876

出　　处：《电路与系统学报》2003年第4期95-99,共5页Journal of Circuits and Systems

摘　　要：在软件无线电系统中,由于A/D输出数据流的采样率很高以及信道选择滤波器过渡带宽要求很窄等原因,数字下变频器(DDC)的运算复杂度很高。该文将基于频率响应屏蔽(FRM)方法的FIR滤波器引入到数字下变频器设计中,并详细地研究了此类数字下变频器的高效实现结构和算法复杂度。理论分析与仿真结果表明文中给出的DDC实现结构的计算效率很高。In a software radio system, the sample rate of the A/D output data is very high and the relative transition width of the filter for extracting a channel is required to be very narrow. Above requirement leads to very high computational complexity in the digital down-converter (DDC). Accordingly, a FIR filter based on frequency response masking technique is introduced into the design of digital down-converters, its efficient implementation architecture is given and the complexity of the algorithm are studied thoroughly. The results of theoretical analysis and simulation show that using the proposed DDC implementation scheme, very high calculation efficiency can be achieved.

关 键 词：数字下变频器(DDC) 频率响应屏蔽技术(FRM) 软件无线电 多速率信号处理 

分 类 号：TN911.72[电子电信—通信与信息系统]