物理层与链路层间接口转换逻辑的设计与实现  

Design and Implementation of High Speed Interface Conversion between Physical Layer and Link Layer

作　　者：陆增援[1] 陈曦[1] 吴义宝[1] 安琪[1] 

机构地区：[1]中国科技大学近代物理系,合肥230027

出　　处：《数据采集与处理》2003年第3期351-355,共5页Journal of Data Acquisition and Processing

摘　　要：论述了物理层的 IX BUS总线与链路层的 POS PHY接口之间的接口转换逻辑的设计 ,详细介绍了 IXBUS总线接口逻辑设计和 POS PHY接口逻辑设计 ,包括时钟设计的实现、虚拟输出队列的实现、POS PHYLEVEL3接口控制的实现和 IX BUS总线 BURST方式的逻辑实现。使用 FPGA实现整个接口转换逻辑 ,经过功能自环测试、与其他通信设备对接测试、与通信测试设备对接测试和严格的温度实验 ,包括循环温度实验和极限温度实验 ,验证了接口转换逻辑的正确性和稳定性。The design and the implementation of logical circuit between POS PHY and IX BUS are studied. It is a design of data conversion between link layer and physical layer. The structure of system and the basic functions of interface logic are described, some key technology, such as clock design and VOQ design, are introduced. Experimental results in the actual system are obtained. Results show that the method of data conversion by the logic and the realization in a single FPGA is feasible and reliable.

关 键 词：宽带网络 物理层 链路层 接口转换逻辑 设计 网络通信 

分 类 号：TN915.142[电子电信—通信与信息系统] TP393[电子电信—信息与通信工程]