卷积码编码器和Viterbi译码器的FPGA实现  

Implementation of convolutional code encoder and Viterbi decoder based on FPGA

作　　者：孙磊[1] 

机构地区：[1]安徽省蚌埠铁路分局职工培训中心,蚌埠233008

出　　处：《信息技术》2003年第10期7-9,22,共4页Information Technology

摘　　要：介绍了目前在数字无线通信中常用的一种向前纠错编码卷积码编码和Viterbi解码的原理,并采用TOP-DOWN的设计思想,利用相关的EDA工具软件进行设计。并将卷积码编码器、Viterbi译码器设计下载到Altera公司的FPGA芯片上进行仿真,得到了预期的设计结果。The article introduces the theory of forward-correcting convolutional code encoder and Viterbi decoder in the digital wireless communication. With the designing concept of top-down,it is designed by utili-zing the related EDA softwares. The designs of encoder and decoder are simulated and tested on FPGA develo-ping board produced by Altera, and the results of the designs are what I expected.

关 键 词：卷积码 编码 解码 

分 类 号：TN911.22[电子电信—通信与信息系统]