基于制作离散性对策的高性能CMOS DAC  

High-Performance CMOS D/A Converter Based on Offsetting Variations in Processing

作　　者：于雪峰[1] 石寅[1] 

机构地区：[1]中国科学院半导体研究所,北京100083

出　　处：《Journal of Semiconductors》2003年第11期1211-1216,共6页半导体学报（英文版）

基　　金：国家高技术研究与发展计划资助项目(编号 :2 0 0 2 AA1Z12 0 0 )~~

摘　　要：基于 CMOS器件的离散性机理及误差消除对策 ,研究了高速、高精度嵌入式 CMOS数 /模转换器 (DAC) IP核的设计与实现 .采用行、列独立译码的二次中心对称电流源矩阵结构 ,优化了电流源开关电路结构与开关次序 ;利用 Cadence的 Skill语言独立开发电流源矩阵的版图排序和布线方法 .在 0 .6 μm N阱 CMOS工艺平台下 ,12 - bitDAC的微分线性误差和积分线性误差分别为 1L SB和 1.5 L SB,在采样率为 15 0 MHz、工作电源为 3.3V时的平均功耗为 14 0 m W.流片一次成功 。The design and implementation of high speed,high accuracy embedded CMOS D/A converter(DAC) IP core are presented,which is based on the principle of variations of CMOS devices and the method to offset the errors.It is implemented in a double centroid current steering architecture with the rows and the columns decoded separately,and the current source switching circuit and the switching sequence are optimized.Cadence Skill language is used to develop the sorting and routing methods of the current source matrix in layout.The 12 bit DAC was integrated in a standard 0 6μm N well CMOS process and the anticipated integral and differential nonlinearity performances are 1LSB and 1 5LSB,respectively.With a supply of 3 3V and sampling rate of 150MHz,the average power consumption is 140mW.The DAC is successfully fabricated and the main specifications meet the expectations.

关 键 词：D/A转换器 CMOS混合集成电路 制作工艺离散性 中心对称 Skill语言 

分 类 号：TN432[电子电信—微电子学与固体电子学]