一种基于扩展查询表的可编程逻辑单元  

An ELUT-Based Programmable Logic Cell

作　　者：郭斌林[1] 童家榕[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《计算机学报》2003年第10期1372-1378,共7页Chinese Journal of Computers

基　　金：国家自然科学基金 ( 60 0 760 14 );高等学校博士点专项基金 ( 2 0 0 0 0 2 462 3 )资助

摘　　要：　通过把 3输入查询表 ,展开为 7输入扩展查询表 ,提出了一种基于扩展查询表的可编程逻辑单元新结构 .通过对扩展查询表进行功能扩展和优化 ,并加入专用快速进位链、专用级联链等功能 ,使得该结构不仅可实现任意3输入 ,部分 4～ 7输入函数 ,而且也能实现快速的算术及高扇入的逻辑 .整个单元组合部分的元件开销小于一个 4输入的查询表 .与相关商用FPGA单元结构进行的比较表明 ,该文提出的单元结构不仅占用的芯片面积较小 ,而且在速度和逻辑实现的能力上都有较大的优势 .Programmable Logic Cells (LCs) play an important role in Field Programmable Gate Array (FPGA). Its performance will influence the whole performance of FPGA. So LC and the design method of its architecture is the important content in FPGA research. In this paper, n-input Look-Up Table (n-LUT) is expanded to be an Extended LUT (ELUT) by Shannon formula. The ELUT can not only implement all n-input functions, but also realize partial (n+1)～(2n-1) input functions. Thus the capacity of implementing function is enhanced under the condition of not increasing MOS transistor. By these characteristics, one 3-LUT is expanded to be 7-ELUT by Shannon formula. Then an ELUT-based LC architecture is presented by function enhancement and optimization based on one-bit Full Adder (FA) including adding fast carry chain, special cascade chain, and so on. The ELUT-based LC can not only implements arbitrary 3-input and partial 7-input function, but also realizes fast arithmetic and high fan input logic function. The LC is consists of the ELUT-based combination logic, sequence logic, cascade logic, etc. Besides general combination logic, the LCs can also implement fast datapath application logics availably such as fast full adder, multiplier, shifter and so on with fast carry chains. In additional, two cascade logics in the LC can support fast high fan logic function effectively so as to support implementing general combination logic and Finite State Machine (FSM) well. By compared with existing commercial FPGA, the LC occupies little chip area and is less MOS transistors. FPGA, be made up of the LC, can economize 40% MOS transistors compared with commercial FPGA when some important logic including datapath application logics are implemented. And one of the LCs is less than a 4-LUT too. Otherwise, the LC has favorable expansibility, regular architecture, and can be mapped easily with CAD tools. The experiments show that the LC architecture has excellent capacity of implementing function, and fast logic speed.

关 键 词：FPGA 可编程逻辑单元 扩展查询表 可编程逻辑器件 

分 类 号：TP332.1[自动化与计算机技术—计算机系统结构]