FPGA开关块拓扑的评估  

Evaluation of FPGA switch block topology

作　　者：高海霞[1] 杨银堂[1] 郑泉智[1] 

机构地区：[1]西安电子科技大学微电子研究所,陕西西安710071

出　　处：《西安电子科技大学学报》2003年第6期752-755,共4页Journal of Xidian University

基　　金：微电子预研资助项目(41308010205)

摘　　要：分析了3种不同开关块的单一布线能力,并使用CAD工具模拟了开关块拓扑对整个现场可编程门阵列布线面积和关键路径延时的影响.模拟结果表明,Wilton开关块有最好的面积有效性,通用开关块次之,不相交开关块的面积有效性最差.然而,开关矩阵类型对电路延时特性的影响很小.还得出一个重要结论:单一开关块的布线能力并不能完全说明开关块拓扑的好坏.The switch block is one of the key units in FPGA. Three different single switch blocks are discussed through illation in the paper. The impact of switch block topology on FPGA area and critical path delay is simulated using CAD tools. Simulation results show that the Wilton switch block appears the most areaefficient, followed by the Universal block, and the Disjoint block has the worst areaefficiency. But we also find that the switch block has little impact on the delay character. Finally, we draw an important conclusion that the routability of a single switch block can not completely represent the quality of switch block topology.

关 键 词：FPGA 开关块 现场可编程门阵列 面积有效性 电路延时 

分 类 号：TN791[电子电信—电路与系统]