多光口SDH网元中DCC通道速率适配电路的设计与实现  

Design of DCC multiplexer used in complex SDH network elements

作　　者：乔庐峰[1] 王志功[1] 经继松[2] 黄颋[1] 王晓明[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096 [2]解放军理工大学通信工程学院,南京210007

出　　处：《东南大学学报（自然科学版）》2003年第6期703-706,共4页Journal of Southeast University：Natural Science Edition

摘　　要：采用现场可编程门阵列 (FPGA) ,设计了一种用于SDH传输系统中数据通信通道 (DCC)数据帧汇聚与速率适配的电路 .可以将具有不同时钟的 1 2个独立DCC通道中的HDLC数据帧进行提取、缓存并复接成一个时分复用的高速数据链路 ,交给MotorolaMPC860中的多通道通信控制器进行处理 .整个设计采用一片XILINX的xc2s2 0 0pq2 0 8完成 ,使用约 1 7万等效门 ,在HDLC最大帧长为 1kB的情况下 ,允许的多通道通信控制器与DCC通道时钟之间的时钟偏差大于 1 4%。This paper presents a new method used in SDH transmission systems to converge the HDLC data frames from 12 independent data communication channels (DCC) into one time-division multiplexing data link. HDLC packets from DCC channels with different clocks can be abstracted, buffered, and inserted into different timeslots of a high speed data link and sent to the multi-channel HDLC controller embedded in the Motorola MPC860 processor. The design is implemented with an XILINX xc2s200pq208 and approximately 170000 equivalent gates are possessed. With HDLC packet length less than 1 kbytes, the tolerance of clock difference between the multi-channel HDLC controller and DCC channels can exceed 1.4%. The tested waveform is presented.

关 键 词：现场可编程门阵列 同步数字序列 高级数据链路控制 数据通信通道 网络管理 

分 类 号：TN722[电子电信—电路与系统]