一种新的2.45GHz频率综合器设计与实现  

Design and Implementation of a Novel 2.45 GHz Frequency Synthesizer

作　　者：马硝霞 万美琳 白创[1] 戴葵[1] 

机构地区：[1]华中科技大学光学与电子信息学院,湖北武汉430074

出　　处：《微电子学与计算机》2014年第7期52-57,共6页Microelectronics & Computer

基　　金：湖北省自然科学基金(ZRZ0051);武汉市科技攻关重点项目(201150699190)

摘　　要：提出了一种新的基于数字FLL的高速、低功耗2.45GHz频率综合器结构,它由鉴频器、数字控制电路、电流控制振荡器组成.它采用高速鉴频器对振荡器输出信号计数实现鉴频,数字控制电路根据鉴频结果调节振荡器输出信号频率来实现输出信号频率与目标频率的锁定.高速分频器基于异步计数结构,降低了内部模块工作频率,使得系统性能稳定;数字控制电路采用逐次逼近算法,使得锁定速度快;基于差分电流饥饿延迟单元的电流控制振荡器采用电流-电容双控模式,使得输出频率调节范围宽、精度高.该电路结构简单,易于实现,版图面积为13 200μm2.在0.18μm工艺下,仿真结果显示,其锁定时间为14μs;输出频率调节范围为1~4.5GHz;输出频率锁定2.450GHz;功耗为4.622mW.In this paper ,a new 2 .45 GHz high-speed low-power frequency synthesizer structure based on FLL is proposed .It is composed of a frequency detector ,digital control circuit and a current-controlled oscillator .The high speed frequency detector is used to detect the oscillator output frequency ,and the digital control logic is used to adjust the frequency of the oscillator output signal according to the frequency detected results so as to achieve the synchronization between the output frequency and the target frequency .The high speed frequency detector is based on a asynchronous counting structure which can reduce the operating frequency of the internal module and thus make the system stable;digital control circuit uses successive approximation algorithm ,making the locking speed fast ;current-controlled oscillator based on differential current-starved delay cell uses current-capacitor dual control mode so as to achieve wide output frequency tuning range and high accuracy .The circuit structure is simple and the layout area is 13 200 μm2 .The simulation results in CMOS 0 .18 μm process show that the locking time of the proposed frequency synthesizer is 14 μs ,tuning range of the output frequency is from 1 GHz to 4 .5 GHz ,and the locked frequency is 2 .45 GHz with the power consumption of 4 .622 mW .

关 键 词：电流控制振荡器 差分电流饥饿型延迟单元 鉴频器 真单相时钟触发器 逐次逼近 

分 类 号：TN74[电子电信—电路与系统]