空域滤波算法硬件化设计  

Hardware Design of Spatial Filtering Algorithm

作　　者：赵东晓[1] 桑红石[1] 

机构地区：[1]华中科技大学自动化学院多谱信息处理技术国家级重点实验室,湖北武汉430074

出　　处：《微电子学与计算机》2014年第8期20-24,共5页Microelectronics & Computer

基　　金：总装预研教育部支撑计划重点项目"微型XXXX光电子系统集成技术"(625010107)

摘　　要：分析了目标识别图像底层预处理的几种常用算法,提出窗口空域滤波计算模型,并采用VerilogHDL语言设计了空域滤波类算法的实时实现硬件结构.该结构具有良好可配置性,用户可以根据自己的需求选择相应的滤波处理方法和计算参数.目前,已经完成了相关模块的结构设计、RTL代码编写、功能验证等数字IC前端设计流程.在SMIC.18μm CMOS工艺下完成了电路综合、形式验证,在120MHz时钟约束下得到运算模块面积约为1.9mm2,相当于114.2k个等效门,功耗为30mW.与公开发表的类似设计相比,我们的设计具有速率快、功耗低、可配置性强的优点.In this paper ,we analysis several bottom processing algorithms on target recongnition and propose spatial filtering calculation model ,and implement a set of real-time hardware architecture for spatial filtering algorithms with VerilogHDL .The advantage of this structure is that it has a good configurability which can make users to choose proper filtering methods and calculated parameters according their needs .At present ,we have completed digital IC front-end design process of the module ,such as the structure design ,RTL coding ,function verification , etc .Simultaneously ,we completed the work of Circuit synthesis and formality verification with Design Compiler Under the SMIC 0 .18 μm CMOS process ,and obtained the area and power are 1 .9 mm2 equal to 114 .2 kGates ,30 mW respectively at the frequency of 120 M Hz .The design has fast speed , low-power , highly configurable advantages compared with the published similar designs .

关 键 词：图像滤波 空域滤波 可配置性 延迟线 

分 类 号：TP391.41[自动化与计算机技术—计算机应用技术]