轻量级AES加解密芯片设计与实现  

The Light-Weight AES Encryption and Decryption Chip Design and Implementation

作　　者：彭浩[1] 刘恺[1] 张亮[1] 廖望[1] 戴葵[1] 

机构地区：[1]华中科技大学光学与电子信息学院,湖北武汉430074

出　　处：《微电子学与计算机》2014年第8期94-97,103,共5页Microelectronics & Computer

基　　金：湖北省自然科学基金(ZRZ0051)

摘　　要：为满足资源受限环境下的安全加解密芯片的设计要求,提出了一种轻量级AES加解密实现方法.该方法采用8位串行数据通路,模块复合结构,并对加解密过程中的状态矩阵、列混合模块和密钥扩展模块的设计优化,用最少的硬件资源实现加解密功能,有效地提高硬件利用率.仿真及实验证明,该设计具有芯片面积小、功耗低的优点,可以满足无线移动网络以及其他资源受限环境.In order to meet the design requirement of security chip with the functions of encryption and decryption under resource-constrained condition , this paper puts forward a light-weight AES encryption and decryption method .With 8-bit serial data path and modular composite structure , this method optimizes state matrix , mixcolumns module and key expansion module in the process of encryption and decryption .It is able to achieve the functions of encryption and decryption with minimal hardware resources and thus effectively improves the hardware utilization .According to simulation and experiment ,the design has the advantages of small chip area and low power consumption ,being available in wireless mobile network and other resource-constrained environments .

关 键 词：AES算法 轻量级 嵌入式系统 复合结构 

分 类 号：TN918.4[电子电信—通信与信息系统]