CADENCE系统上Timing-Driven设计流程探讨  

Study on the Time-Driven Design Flow Based on Cadence System

作　　者：居水荣 张亦斌 郑明 

机构地区：[1]无锡华润矽科微电子有限公司设计所,无锡214061

出　　处：《微电子技术》2003年第6期9-12,共4页Microelectronic Technology

摘　　要：本文首先介绍了亚微米领域集成电路中的寄生参数选取模型 ,然后给出了一种称之为时序驱动的设计流程 ,并对其中的关键步骤和工具作了简要介绍 ,着重介绍了布局布线工具SE中的时序驱动设计方法 。First, the extract model of parasitic parameter in sub-micron area ICs is introduced in this paper. Then, a timing-driven design flow is given, and some critical steps and tools are briefly introduced. The emphasis introduced is timing-driven design method in place and route tools “Silicon Ensemble”. At last, how to build unit timing library is presented in brief.

关 键 词：寄生参数 延时 时序驱动 设计流程 亚微米领域集成电路 CADENCE系统 Timing—Driven 

分 类 号：TN402[电子电信—微电子学与固体电子学]