基于程序切片的电路提取技术  

Automatic Circuit Extraction Using Program Slicing

作　　者：朱丹[1] 李暾[1] 万海[1] 郭阳[1] 李思昆[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《国防科技大学学报》2003年第6期10-15,共6页Journal of National University of Defense Technology

基　　金：国家自然科学基金重点项目基金资助(90207019);863项目基金资助(2002AA1Z1480)

摘　　要：从HDL设计描述中提取电路在VLSI设计验证、低功耗分析、测试生成等方面有广泛的应用需求。提出了一种采用程序切片技术实现的新的电路提取方法,并深入论述了基于程序切片技术从Verilog描述中进行电路提取的理论基础。该方法可以为每一个感兴趣的信号获取其"链接切片"。与以前的方法相比,该方法的优点是细粒度的、不受书写格式的限制,并且能处理更多Verilog的语法元素。该方法已经被集成到现有设计流程中,实验结果表明其方便、高效,有良好的通用性。The design extraction from HDL description has been greatly needed in modern VLSI design process,such as the design (verification),low power analysis,test generation and so on.This paper presents a new circuit extraction method using (program) (slicing) (technique),and develops an elegant theoretical basis, based on program slicing, for circuit extraction from Verilog (description. With) (the) (technique we) (can) obtain a 'chaining slice' for each given signal of interest.Our method has advantage in its fine grain,without (writing-style) (limitation) (and) in dealing with more Verilog components characteristics.The technique has been used in the design process and the (results) (show) (its) (convenience),efficiency and good practicability.

关 键 词：程序切片 链接切片 进程依赖图 电路提取 

分 类 号：TP302.7[自动化与计算机技术—计算机系统结构]