一种支持高效加法的FPGA嵌入式DSP IP设计  

A design of FPGA embedded DSP IP core supporting efficient addition

作　　者：王楠[1,2] 黄志洪[1] 杨海钢[1,2] 丁健[1] WANG Nan;HUANG Zhihong;YANG Haigang;DING Jian(System on Programmable Chip Research Department,Institute of Electrics,Chinese Academy of Sciences,Beijing100190,China;University of Chinese Academy of Sciences,Chinese Academy of Sciences,Beijing100049,China)

机构地区：[1]中国科学院电子学研究所,北京100190 [2]中国科学院中国科学院大学,北京100049

出　　处：《太赫兹科学与电子信息学报》2017年第5期867-873,共7页Journal of Terahertz Science and Electronic Information Technology

摘　　要：提出了一种支持可变位宽高效加法的现场可编程逻辑门阵列(FPGA)嵌入式数字信号处理(DSP)单元知识产权(IP)硬核结构,相比于Altera公司的Stratix-Ⅲ DSP结构,基于本文提出的优化结构可以更高效地实现加法、乘加以及累加等多种应用。利用软件对不同数据类型和位宽的输入实现数据预处理,减小了硬件资源的开销,并进一步提升了电路性能。同时在DSP结构中加入了乘法旁路器和二级符号位扩展的加法电路,在减小DSP实现面积的同时,支持超高位宽、高速的流水线型加法运算,扩展了DSP的应用范围。采用TSMC 55 nm标准CMOS工艺设计并完成了所提出的DSP IP核的电路实现,可实现包括72位可变位宽加法及36位可变位宽乘法等在内的9种运算模式。An embedded Field-Programmable Gate Arrays(FPGA)Digital Signal Processor(DSP)core’s architecture which supports efficient width variable addition is presented.Compared with the Stratix-ⅢDSP core of Altera corporation,the optimized architecture will give higher efficiency to a variety of applications such as addition,multiply-addition and accumulation.It can not only reduce the circuit area but also improve the circuit performance by using software to pre-process the data with different types and bit-width.Meanwhile,a multiply-bypass circuit and two-stage sign extensional addition circuit are added to the DSP core,which implements a high bit-width,high-speed pipelined operation and reduces the circuit area as well.The design of DSP IP(Intellectual Property)core utilizes TSMC 55 nm CMOS technology,which supports nine-operation modes including 72 bit addition and 36 bit multiplication for variable width inputs.

关 键 词：现场可编程逻辑门阵列(FPGA) 嵌入式DSP 加法运算 乘法旁路器 符号位扩展 

分 类 号：TN791[电子电信—电路与系统] TP332[自动化与计算机技术—计算机系统结构]