一种减小正码速调整等候抖动的新方法  

A New Method for Reducing the Waiting Jitter of Positive Justification

作　　者：曾烈光[1] 冯重熙[1] 

机构地区：[1]清华大学

出　　处：《通信学报》1992年第1期45-51,共7页Journal on Communications

摘　　要：本文提出一种能够明显减小正码速调整等候抖动的新方法——分离塞入比法。采用此方法的超大规模专用集成电路已在日本制成。本文简介这种方法提出的背景、原理、实验结果及应用特点。This paper presents a new method which can be used to obiviously reduce the waiting jitter in positive justification by means of splitting stuff ratio of positive justification. The VLSI designed for this method has been made in Japan.This paper describes the principle of this method and the experiment results. Finally, the application of this method will be briefly introduced.

关 键 词：正码速调整 抖动 减小 分离塞入比 

分 类 号：TN762[电子电信—电路与系统]