一种RSA算法的新型ASIC实现  

A New ASIC Implementation of RSA Algorithm

作　　者：朱柯嘉[1] 杨青松[1] 徐科[1] 闵昊[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《复旦学报（自然科学版）》2004年第1期16-20,共5页Journal of Fudan University：Natural Science

摘　　要：提出了一种实现RSA算法的新型ASIC结构,具有较小的芯片面积和较强的灵活性,适合于智能IC卡应用.利用0.5μmCMOS标准单元库实现了该RSA协处理器,约折合14K(210)等效门,面积约3mm2,最高工作频率40MHz,完成1024位RSA加/解密运算需时375ms.A new ASIC implementation of RSA algorithm is presented. It has less area and more flexibility, making the chip very suitable for smart card applications. The RSA coprocessor has been implemented by using 0.5 μm CMOS standard cell library. The coprocessor has 14 K gates count and 3 mm^2 die size with a maximum clock frequency 40 MHz, which takes about 375 ms to encrypt/decrypt 1024-bit data.

关 键 词：专用集成电路 RSA算法 协处理器 智能IC卡 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]