通过抖动建模和分解计算高速计算机系统的误码率  

Predict High-speed Computer System Bit Error Rate Through Timing Jitter Model and Decomposition

作　　者：张楷[1] 汤志忠[1] 

机构地区：[1]清华大学计算机科学与技术系,北京100084

出　　处：《计算机工程与应用》2004年第8期50-53,共4页Computer Engineering and Applications

基　　金：国家自然科学基金资助项目(编号:60173010)

摘　　要：随着计算机速度的显著提高,定时抖动已经成为影响高速计算机性能的基本因素,文章全面介绍了如何根据抖动中的具体参数进行抖动可视化和抖动建模,进而进行抖动分解,运用统计学的方法,将高速计算机系统中的抖动进行时域和频域的分析,通过计算抖动来估算系统的误码率。最后对随机抖动和确定性抖动分量分离给出了一种实际可行的抖动分解和测试方法。As computer signal rates climb above1GHz and voltage swings shrink to conserve power,the timing jitter in a high-speed computer system becomes a significant percentage of the signal interval.Under these circumstances,jitter becomes a fundamental performance limit.The article analyzes the form of jitter visualization and jitter mathematical model by using the statistic terms.Through making the time and frequent demain analysis,the timing jitter could be de-composed and predict computer system performance and bit error rate.In the end,the article provides a practical method to characterize the timing jitter and bit error rate.

关 键 词：确定性抖动 随机性抖动 数据相关抖动 误码率 时间间隔误差 

分 类 号：TP33[自动化与计算机技术—计算机系统结构]