用于基站通信的ADSP Tiger SHARC 101S数字信号处理器  

ADSP tiger sharc 101S digital signal processorin base station communication

作　　者：任磊[1] 

机构地区：[1]空军雷达学院科研部,湖北武汉430010

出　　处：《半导体技术》2004年第4期65-68,共4页Semiconductor Technology

摘　　要：ADSP Tiger SHARC 101S数字处理器是美国Analog Device公司最新推出的定/浮点信号处理器。该处理器对大的信号处理任务和通信结构进行了专门的优化,能够方便实现多片并行处理系统扩展。本文详细介绍了其主要性能及结构特点,并给出由该处理器构成的带外部SDRAM系统结构。ADSP Tiger SHARC 101S digital processor is the latest high-performance fixed/floatingpoint DSP which is presented after the 16-bit fixed point ADSP21xx and 32-bit floating point ADSP21xxxby Analog Device Inc. Special optimization is adapted to use communication structure and work ingreat signal procession task, which makes it easy to realize paratactic multi-processors system. Theperformance and structure characteristics of the processor are introduced in details, and typicalADSP Tiger SHARC 101S system structure with external SDRAM is given for reference.

关 键 词：基站 数字信号处理器 SDRAM ADSP TIGER SHARC1O1S 浮点运算 

分 类 号：TN911.72[电子电信—通信与信息系统] TN929.5[电子电信—信息与通信工程]