甚短距离光传输系统并行帧同步电路的设计与实现  

Design and Implementation of a Parallel Frame Aligner in VSR System

作　　者：曾敏[1] 朱恩[1] 王晓明[1] 苗澎[1] 王志功[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,江苏省南京市210096

出　　处：《电子工程师》2004年第4期26-29,共4页Electronic Engineer

基　　金：国家高技术研究发展计划 (863计划 )(2 0 0 1AA12 2 0 3 2 )

摘　　要：根据甚短距离 (VSR)光纤传输系统中转换接收芯片帧同步系统的设计思想 ,参考ITU T关于同步数字系列 (SDH)技术的建议 ,分析了帧同步系统的关键性能参数 ,结合具体硬件电路的设计 ,选取了合适的参数。在此基础上 ,用VerilogHDL语言设计了帧同步系统 ,选用Altera公司的StratixEP1S2 5F780C5 ,对电路进行了仿真模拟。作为VSR实验系统关键电路之一 ,帧同步系统通过在系统测试 ,测试结果显示该帧同步系统能够在实际中应用。Basing on the design philosophy of the frame aligner in receive module of conversion IC in VSR optical transmission system, and according to the recommendation of ITU T about SDH, several parameters, which are important to the performance of the frame aligner, are analyzed and chosen with consideration of the circuit used. Basing on the analysis, the frame aligner is designed using Verilog HDL, and FPGAs of Stratix EP1S25F780C5 from Altera corporation. As one of the important parts of the VSR experimental system, the simulation and downloading to the device are accomplished. It is demonstrated that the design of the frame aligner is applicable to the VSR system.

关 键 词：甚短距离光传输系统 帧同步 同步数字系列 现场可编程门阵列 

分 类 号：TN929.11[电子电信—通信与信息系统]