异步时序逻辑电路设计的一种简明方法  

Simple Method to Design Asynchronous Sequential Logic Circuit

作　　者：赵兴强[1] 

机构地区：[1]西华师范大学计算机科学系,四川南充637002

出　　处：《西华师范大学学报（自然科学版）》2004年第2期227-230,共4页Journal of China West Normal University(Natural Sciences)

摘　　要：提出了一种异步时序电路设计的新方法:时钟信号与次态卡诺图联立法.根据时钟信号填写次态卡诺图,当触发器满足时钟信号时其次态由状态转换图决定,否则其次态为约束项.据此可方便求出驱动方程并判断自启动.This paper presents a new method to design asynchronous sequential circuit:clock signals and secondary state Karnaugy Map uniting method.A secondary Karnaugh Map is filled in based on clock signals,when the filp-flop satisfies the clock signals ,its state follows the state-shift map.If not ,the latter is a restrictive item.On these grounds ,drive equation can be easily deduced .Then we can judge whether the circuit can start automatically.

关 键 词：异步时序逻辑电路 电路设计 时钟信号 次态卡诺图 状态转换图 约束项 

分 类 号：TP331.1[自动化与计算机技术—计算机系统结构]