一种高效率MCS51兼容型微控制器内核设计  

Design of a High-Efficiency MCS51 Compatible MCU Core

作　　者：杨浩[1] 林争辉[1] 李世煜[1] 

机构地区：[1]上海交通大学电子工程系,上海200030

出　　处：《微电子学与计算机》2004年第5期166-168,共3页Microelectronics & Computer

基　　金：国家863基金资助项目(2002AA1Z1190)

摘　　要：在对传统的MCS51微处理器的局限性进行分析的基础上,提出了一种高效率、低功耗、适合于SoC应用的改进的MCS51兼容型嵌入式微控制器。该控制器采用流水线结构和两相时钟,指令效率提高了12倍。在兼容原有指令集的基础上进行了扩充,提升了特定应用的效率。增加电源管理机制,提供了低功耗待机状态。在AlteraFPGA上验证,此MCU可稳定工作于33MHz时钟频率。Based on the analysis of the limitation of the MCS51 MCU, a high-efficiency and low-power MCU, which is compatible with MCS51, is designed. The efficiency of the instruction is improved by 12 times by optimizing the pipeline structure and two phase clock. The instruction set is extended in order to improve the efficiency in particular application. The MCU supply the sleep-mode to decrease the power consumption by adds a new power management controller. Altera FPGA verification and simulation shows that the MCU can run at 33MHz clock frequency steadily.

关 键 词：类RISC 嵌入式微控制器 直通结构 流水线 低功耗 

分 类 号：TN47[电子电信—微电子学与固体电子学]