基于北斗/GPS秒脉冲的高稳时钟源设计  

Design of High Stable Clock Source Based on Beidou/GPS Second Pulse

作　　者：杨建国 傅瑞峰 黄旭方[1] 

机构地区：[1]广西大学,计算机与电子信息学院,广西南宁

出　　处：《计算机科学与应用》2017年第1期1-7,共7页Computer Science and Application

基　　金：国家自然科学基金(61004123);广西大学大学生创新项目(T3070098228)。

摘　　要：基于UM220IIIN双系统接收机和FPGA,设计一种北斗/GPS秒脉冲高稳同步时钟源。利用两块UM220IIIN分别接收北斗和GPS秒脉冲[1],将秒脉冲输入到FPGA的cyclone IV芯片,先分别对两路秒脉冲信号进行有效性判断。若两路秒脉冲都有效,则在10秒内对它们分别进行的高频计数,计数基准是利用FPGA内部自带的高频时钟;若只有一路有效,就只对有效支路进行高频计数。然后求取10秒内计数值的均值和方差,通过比较两路秒脉冲的方差,输出最优一路的秒脉冲;或输出其中有效支路的秒脉冲均值。当北斗和GPS秒脉冲都失效时,利用FPGA内部自带的高频时钟以及历史数据,预测下一时刻的秒脉冲输出周期,系统可以继续输出高精度的秒脉冲作为时钟源。Based on the UM220IIIN double system receiver and FPGA, a clock source of the Beidou or GPS second pulse high stability is designed in this paper. Two UM220IIIN receive the second pulse of  Beidou satellite and GPS, inputting to the cyclone IV chip of FPGA, and then it is first to judge the validity of the second pulse signal of Beidou and GPS. If the two second pulses are valid, they were carried out by the high frequency count in 10 seconds, and counting is based on the use of FPGA internal own high-frequency clock;if only one way is valid, only the effective second pulse is counted. Then calculating the mean and variance of the count in 10 seconds, the best second pulse or the effective branch of the second pulse is output by comparing the variance of the second pulse. If the second pulse of Beidou satellite and GPS are invalid and the use of FPGA internal clock and historical data predict next output cycle of the second pulse, the system can continue to output high precision of the second pulse as a clock source.

关 键 词：时钟源 北斗 GPS FPGA 

分 类 号：TN7[电子电信—电路与系统]