同步TP RAM的低功耗设计方法  

A Low Power Design Method for Synchronous TP RAM

作　　者：周新格 周清军[2] 

机构地区：[1]西安高新唐南中学,陕西西安 [2]西安培华学院中兴电信学院,陕西西安

出　　处：《电路与系统》2017年第2期40-46,共7页Open Journal of Circuits and Systems

摘　　要：针对SoC中同步TP RAM的功耗较大问题,提出一种设计方法。通过将SoC中的同步TP RAM替换成SP RAM,在SP RAM外围增加读写接口转换逻辑,使替换后的RAM实现原TP RAM的功能,保持对外接口不变。为了进一步降低功耗,对地址总线进行格雷编码,采用动态电压调整技术及合理的电源分区策略。将文中方法应用于一款多核SoC芯片,经TSMC 28 nm HPC工艺实现。仿真结果表明:优化后的RAM面积减少了24.76%,功耗降低了44.89%。As the power consumption of synchronous TP RAM in SoC is large, a new design method of opti-mization is proposed. In order to achieve the function of the original TP RAM and keep the exter-nal interface unchanged, TP RAM is replaced with SP RAM, and read-write interface logics of con-version are added around SP RAM. For less power, address bus is encoded through Gray code;dynamic voltage regulation and reasonable power partition strategy are used. The method discussed in this paper is used in the multi core SoC chip which has been implemented in TSMC 28nm HPC process. The simulation results indicate that the area of optimized RAMs is reduced by 24.76%, and the power saving is reduced by 44.89%.

关 键 词：同步TP RAM SP RAM 格雷码 动态电压调整 电源分区策略 

分 类 号：TP33[自动化与计算机技术—计算机系统结构]