Leakage Analysis of a Low Power 10 Transistor SRAM Cell in 90 nm Technology  

作　　者：Parimaladevi Muthusamy Sharmila Dhandapani Parimaladevi Muthusamy;Sharmila Dhandapani(Department of Information and Communication Engineering, Anna University, Chennai, India;Department of Electronics and Instrumentation Engineering, Bannari Amman Institute of Technology, Sathyamangalam, India)

机构地区：[1]Department of Information and Communication Engineering, Anna University, Chennai, India [2]Department of Electronics and Instrumentation Engineering, Bannari Amman Institute of Technology, Sathyamangalam, India

出　　处：《Circuits and Systems》2016年第6期1033-1041,共9页电路与系统（英文）

摘　　要：In this paper, a novel 10 Transistor Static Random Access Memory (SRAM) cell is proposed. Read and Write bit lines are decoupled in the proposed cell. Feedback loop-cutting with single bit line write scheme is employed in the 10 Transistor SRAM cell to reduce active power consumption during the write operation. Read access time and write access time are measured for proposed cell architecture based on Eldo SPICE simulation using TSMC based 90 nm Complementary Metal Oxide Semiconductor (CMOS) technology at various process corners. Leakage current measurements made on hold mode of operation show that proposed cell architecture is having 12.31 nano amperes as compared to 40.63 nano amperes of the standard 6 Transistor cell. 10 Transistor cell also has better performance in terms of leakage power as compared to 6 Transistor cell.In this paper, a novel 10 Transistor Static Random Access Memory (SRAM) cell is proposed. Read and Write bit lines are decoupled in the proposed cell. Feedback loop-cutting with single bit line write scheme is employed in the 10 Transistor SRAM cell to reduce active power consumption during the write operation. Read access time and write access time are measured for proposed cell architecture based on Eldo SPICE simulation using TSMC based 90 nm Complementary Metal Oxide Semiconductor (CMOS) technology at various process corners. Leakage current measurements made on hold mode of operation show that proposed cell architecture is having 12.31 nano amperes as compared to 40.63 nano amperes of the standard 6 Transistor cell. 10 Transistor cell also has better performance in terms of leakage power as compared to 6 Transistor cell.

关 键 词：SRAM Transmission Gate Subthreshold Leakage Gate Leakage Read Access Time Write Access Time 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]