NP-Domino, Ultra-Low-Voltage, High-Speed, Dual-Rail, CMOS NOR Gates  

作　　者：Ali Dadashi Omid Mirmotahari Yngvar Berg Ali Dadashi;Omid Mirmotahari;Yngvar Berg(Nanoelectronics Research Group, Department of Informatics, University of Oslo, Oslo, Norway)

机构地区：[1]Nanoelectronics Research Group, Department of Informatics, University of Oslo, Oslo, Norway

出　　处：《Circuits and Systems》2016年第8期1916-1926,共11页电路与系统（英文）

摘　　要：In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.

关 键 词：Ultra Low Voltage (ULV) Semi-Floating-Gate (SFG) Speed NOR Gate Monte Carlo TSMC 90 nm CMOS 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]