Capacitor Pattern H-Bridge Multilevel Inverter (CPHMLI) Using Phase Diposition Pulse Width Modulation for Grid Applications  

Capacitor Pattern H-Bridge Multilevel Inverter (CPHMLI) Using Phase Diposition Pulse Width Modulation for Grid Applications

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作  者:M. S. Saravanan R. Jeyabharath M. S. Saravanan;R. Jeyabharath(Department of ECE, Mahendra College of Engineering, Salem, India;Department of EEE, KSR Institute for Engineering and Technology, Tiruchengode, India)

机构地区:[1]Department of ECE, Mahendra College of Engineering, Salem, India [2]Department of EEE, KSR Institute for Engineering and Technology, Tiruchengode, India

出  处:《Circuits and Systems》2016年第10期3310-3319,共10页电路与系统(英文)

摘  要:This work presents an implementation of an innovative single phase multilevel inverter using capacitors with reduced switches. The proposed Capacitor pattern H-bridge Multilevel Inverter (CPHMLI) topology consists of a proper number of Capacitor connected with switches and power sources. The advanced switching control supplied by Pulse Width Modulation (PDPWM) to attain mixed staircase switching state. The charging and discharging mode are achieved by calculating the voltage error at the load. Furthermore, to accomplish the higher voltage levels at the output with less number of semiconductors switches and simple commutation designed using CPHMLI topology. To prove the performance and effectiveness of the proposed approach, a set of experiments performed under various load conditions using MATLAB tool.This work presents an implementation of an innovative single phase multilevel inverter using capacitors with reduced switches. The proposed Capacitor pattern H-bridge Multilevel Inverter (CPHMLI) topology consists of a proper number of Capacitor connected with switches and power sources. The advanced switching control supplied by Pulse Width Modulation (PDPWM) to attain mixed staircase switching state. The charging and discharging mode are achieved by calculating the voltage error at the load. Furthermore, to accomplish the higher voltage levels at the output with less number of semiconductors switches and simple commutation designed using CPHMLI topology. To prove the performance and effectiveness of the proposed approach, a set of experiments performed under various load conditions using MATLAB tool.

关 键 词:Switched Capacitor Multilevel Inverter Phase Diposition Pulse Width Modulation Capacitor Pattern Based Multilevel Inverter Total Harmonic Distortion Cascaded H-Bridge 17-Level Inverter 

分 类 号:TN7[电子电信—电路与系统]

 

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