A 500-MS/s, 2.0-mW, 8-Bit Subranging ADC with Time-Domain Quantizer  

作　　者：Kenichi Ohhata Kaihei Hotta Naoto Yamaguchi Daiki Hayakawa Kenji Sewaki Kento Imayanagida Yuuki Sonoda 

机构地区：[1]Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University, Kagoshima, Japan

出　　处：《Circuits and Systems》2017年第1期1-13,共13页电路与系统（英文）

摘　　要：This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. The test chip demonstrated a high sampling frequency of 500 MHz and a low-power dissipation of 2.0 mW, resulting in a low FOM of 32 fJ/conversion-step.This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. The test chip demonstrated a high sampling frequency of 500 MHz and a low-power dissipation of 2.0 mW, resulting in a low FOM of 32 fJ/conversion-step.

关 键 词：Time-Based ADC FLASH ADC TDC VTC CMOS 

分 类 号：TN7[电子电信—电路与系统]