Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation  

作　　者：Agord de Matos Pinto Jr Raphael Ronald Noal Souza Mateus Biancarde Castro Eduardo Rodrigues de Lima Leandro Tiago Manêra Agord de Matos Pinto Jr;Raphael Ronald Noal Souza;Mateus Biancarde Castro;Eduardo Rodrigues de Lima;Leandro Tiago Manêra(School of Electrical and Computer Engineering (FEEC), University of Campinas, Campinas, Brazil;Eldorado Research Institute, Campinas, Brazil)

机构地区：[1]School of Electrical and Computer Engineering (FEEC), University of Campinas, Campinas, Brazil [2]Eldorado Research Institute, Campinas, Brazil

出　　处：《Circuits and Systems》2023年第6期19-28,共10页电路与系统（英文）

摘　　要：This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V_DD = 1.8 V, the resulting set of performance parameters include power consumption P_DC = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P_DC and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V_DD = 1.8 V, the resulting set of performance parameters include power consumption P_DC = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P_DC and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.

关 键 词：Phase Locked Loop (PLL) Voltage-Controlled Ring Oscillators (VCRO) Dual-Delay-Path DDP Delay Cells 

分 类 号：TN7[电子电信—电路与系统]