Simulation Study of Nanoscale FDSOI MOSFET Characteristics  

作　　者：Towhid Adnan Chowdhury Towhid Adnan Chowdhury(Department of Electrical & Electronic Engineering, Ahsanullah University of Science & Technology, Dhaka, Bangladesh)

机构地区：[1]Department of Electrical & Electronic Engineering, Ahsanullah University of Science & Technology, Dhaka, Bangladesh

出　　处：《Soft Nanoscience Letters》2023年第3期13-22,共10页软纳米科学报（英文）

摘　　要：Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate lengths. The performance is compared and contrasted with the help of threshold voltage, subthreshold slope, on-state current and leakage current. Interestingly, by decreasing the gate length, the leakage current and on-state current are increased but the threshold voltage is decreased and the sub-threshold slope is degraded. Silvaco two-dimensional simulations are used to analyze the performance of the proposed structures.Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate lengths. The performance is compared and contrasted with the help of threshold voltage, subthreshold slope, on-state current and leakage current. Interestingly, by decreasing the gate length, the leakage current and on-state current are increased but the threshold voltage is decreased and the sub-threshold slope is degraded. Silvaco two-dimensional simulations are used to analyze the performance of the proposed structures.

关 键 词：Fully Depleted Silicon on Insulator Threshold Voltage Subthreshold Slope Leakage Current Gate Length 

分 类 号：TN3[电子电信—物理电子学]