A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard  

作　　者：Yawen Wang Sini Bin Shikai Zhu Xiaoting Hu Yawen Wang;Sini Bin;Shikai Zhu;Xiaoting Hu(College of Computer Science & Technology, Jiangsu Normal University, Xuzhou, China)

机构地区：[1]College of Computer Science & Technology, Jiangsu Normal University, Xuzhou, China

出　　处：《Journal of Computer and Communications》2024年第4期228-246,共19页电脑和通信（英文）

摘　　要：The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.

关 键 词：Advanced Encryption Standard (AES) S-BOX Tower Field Hardware Implementation Application Specific Integration Circuit (ASIC) 

分 类 号：TN9[电子电信—信息与通信工程]