一种用于Pipeline ADC的高线性度栅压自举开关  

A High Linearity Gate Voltage Bootstrap Switch for Pipeline ADC

作　　者：王巍[1] 税绍林 戴佳洪 赵汝法 刘斌政 袁军[1] 马力 王育新[2] 王妍[2] WANG Wei;SHUI Shaolin;DAI Jiahong;CHIO U-fat;LIU Binzheng;YUAN Jun;MA Li;WANG Yuxin;WANG Yan(College of Electronics Engineering/International Semiconductor College,Chongqing University of Posts and Telecommunications,Chongqing 400065,P.R.China;The 24th Research Institute of China Electronics Technology Group Corp.,Chongqing 400060,P.R.China)

机构地区：[1]重庆邮电大学光电工程学院/国际半导体学院,重庆400065 [2]中国电子科技集团公司第二十四研究所,重庆400060

出　　处：《微电子学》2023年第5期758-763,共6页Microelectronics

基　　金：重庆市科技局产业化项目(CSTC2018JSZX-CYZTZX0211,CSTC2018JSZX-CYZTZX0048);模拟集成电路国家级重点实验室开放项目(2022-JCJQ-LB-049-1);重庆市科技局自然科学基金(CSTB2022NSCQ-MSX1389);重庆市留学人员回国创业创新支持计划(2204012976831207)

摘　　要：在流水线模数转换器(Pipeline ADC)电路中,栅压自举开关中的非线性电容会对开关管的导通电阻产生直接的影响,导致采样非线性。设计了一种三路径的高线性度栅压自举开关,采用三个自举电容,分别构成两条主路径和一条辅助路径,使得输入信号在通过两条主路径传输到开关管栅端时加快栅端电压的建立,同时利用辅助路径驱动非线性电容,减少电路中非线性电容对采样电路线性度的影响,从而增强信号驱动能力,提高整体电路的精度。本文设计的栅压自举开关应用于14 bit 500 MHz流水线ADC的采样保持电路中。采用TSMC 28 nm CMOS工艺进行电路设计。仿真结果表明,在输入频率为249 MHz,采样频率为500 MHz的条件下,该栅压自举开关的信噪比(SNDR)达到92.85 dB,无杂散动态范围(SFDR)达到110.98 dB。In the pipeline ADC circuit,the nonlinear capacitance in the gate-voltage bootstrap switch has a direct effect on the on-resistance of the switch,resulting in nonlinear sampling.In this paper,a three-path gate voltage bootstrap switch with high linearity was designed.Three bootstrap capacitors were used to form two main paths and one auxiliary path,which speeded up the gate voltage establishment when the input signal was transmitted to the gate end of the switch through the two main paths.Thus,the signal driving ability was enhanced and the accuracy of the overall circuit was improved.The designed gate-voltage bootstrap switch was used in the sample-and-hold circuit of a 14 bit 500 MHz pipelined ADC.The circuit was designed in TSMC 28 nm CMOS process.The simulation results show that the signal-to-noise ratio(SNDR)of the proposed gate voltage bootstrap switch is 92.85 dB and the spurious free dynamic range(SFDR)is 110.98 dB when the input frequency is 249 MHz and the sampling frequency is 500 MHz.

关 键 词：栅压自举开关 采样保持电路 非线性电容 主路径 辅助路径 

分 类 号：TN792[电子电信—电路与系统]