基于ASIC/SoC的UART核的设计  

Design of UART core based on ASIC/SoC

作　　者：尧勇仕 顾晓峰[1] 于宗光 韩郑生[2] 

机构地区：[1]江南大学,江苏无锡214122 [2]中国科学院微电子研究所,北京100029

出　　处：《微计算机信息》2008年第5期92-93,205,共3页Control & Automation

基　　金：国防科技重点实验室基金资助项目:(编号不公开);无锡市科技计划项目-青年科技人才创新创业项目(DA050001)

摘　　要：本文描述了通用异步收发机UART(Universal Asynchronous Receive Transmitter)核的一种优化设计实现的设计流程。通过采用划分功能模块使结构直观清晰并且简化了设计流程。该UART核采用VerilogHDL语言描述其功能,对RTL级实现优化,解决了多时钟、亚稳态和毛刺等问题。用SYNOPSYS软件仿真、验证和综合、优化生成的IP(Intellectual Property)核可以很方便地嵌入到ASIC/SoC设计中。This paper presents the design flow of a UART (Universal Asynchronous Receive Transmitter)core by optimized designing and realization. The function module partition method is applied to make the structure clear and to simplify the design flow. The UART core function is described using VerilogHDL language and optimized in the RTL code. Problems such as multiclock,metastable state and burr are solved. The IP (Intellectual Property) core generated by simulation,validation,synthesis and optimiza-tion using SYNO...

关 键 词：UART SOC VERILOGHDL语言 验证与综合 

分 类 号：TN839[电子电信—信息与通信工程]