使用CPLD实现通用串行总线接口收发模块  

Realization of USB Interface Sending and Receiving Module with CPLD

作　　者：赵虹[1] 

机构地区：[1]廊坊武警学院基础部,065000

出　　处：《微计算机信息》2008年第8期215-216,200,共3页Control & Automation

基　　金：公安部科研项目(编号不公开)

摘　　要：本文讨论了使用CPLD实现通用串行总线(USB)接口收发模块的过程,其中包括串行化、位插入、NRZI编码及其解码、反位插入、并行化等步骤,给出了发送模块设计的部分VHDL源代码。各功能单元及顶层文件的VHDL源代码使用MAXPLUSⅡ进行了时序仿真,仿真的结果符合设计要求。该设计最终用可编程逻辑器件EPM3032A实现硬件电路。This paper discussed the realization procedure of Universal Serial Bus sending and receiving module by CPLD.It includes serial access,bit insert,NRZI coding and decoding,inverse bit insert,and parallelization.It gave the method of design sending module. The VHDL fountain code of all function cells and their top document have been simulated by MAXPLUSⅡ in the time_domain,and the result completely satisfied the requirements.At last,the circuit was realized by EPM3032A .

关 键 词：USB接口 NRZI编码 CPLD VHDL 

分 类 号：TN79[电子电信—电路与系统]